SV Visual IDE — SystemVerilog Schematic Editor

SV Visual IDE

Dark Mode

Library

↓ Drag to canvas to place

100%

Drop to place module

Properties

🔲

Select a module or port to view its properties

Click + Module to create your first module

Unsaved Changes

Do you want to download (save) the current project before starting a new one?

All unsaved work will be lost if you discard.

New Project

Start from scratch or pick an example to get started quickly.

SystemVerilog Editor

Ready. Add modules and click Simulate to run.

FPGA Build Terminal. Click "Build FPGA" to synthesize your design for Tang Nano 9K.

Signals

New Module

Module Name Must be a valid SystemVerilog identifier

Parameters (optional) Comma-separated parameter=value pairs

New Signal Driver

Module Name

Bus Width

New LED Display

Module Name

New Clock Source

Module Name Must be a valid SystemVerilog identifier

Frequency

New Reset Source

Module Name Must be a valid SystemVerilog identifier

Active Level

New Signal Monitor

Monitor Name Must be a valid SystemVerilog identifier

Display Label Label shown in simulation console output

Signal Width (bits) 1 = single bit · >1 = bus (e.g., 8 for [7:0])

Connect the probe input port to any signal. Values will appear in the Simulation Console when you run a simulation.

Add Port

Port Name

Direction

Bit Width Number (e.g. 8) or a parameter name (e.g. WIDTH)

✏ Edit Port

Port Name

Direction

Bit Width Number (e.g. 8) or a parameter name (e.g. WIDTH)

Existing connections to this port are preserved — only the name, direction, and width are updated.

Instantiate Module

Instance Name Unique name for this instance

Parameter Overrides (optional) Override the module's default parameters

Choose Module to Instantiate

No other modules available to instantiate.

Choose Top Module

No valid modules found for synthesis.

Tang Nano 9K Pin Mapping

Map your top-level ports to physical pins on the Tang Nano 9K FPGA.
Reference: LED1: Pin 10, LED2: Pin 11, LED3: Pin 13, LED4: Pin 14, LED5: Pin 15, LED6: Pin 16.

Pin Constraints (Tang Nano 9k)

Assign physical pin numbers to the I/O ports of your synthesized design.

Port Name	Direction	Pin Number	IO_TYPE	DRIVE (mA)	SLEW_RATE	OPEN_DRAIN	SINGLE_RESISTOR

No top-level ports found. Please run synthesis first!